A phase-alignment circuit (“PAC”), such as a Phase Lock Loop (“PLL”) or a Delay Lock Loop (“DLL”), is an electronic circuit which generates an output signal that has a well-controlled relationship in phase and frequency to an input signal.
Phase-alignment circuits are used in a variety of electronic devices. For example, a PLL may be used for clock synthesis in a multi-purpose processor. In another example, a PAC may be used in point-to-point communication systems, including serial and parallel systems, where one PAC generates a sampling clock at the receiver while another PAC generates a transmit clock at the output driver of the transmitter.
In testing or troubleshooting a phase-alignment circuit such as a PLL, it may be desirable to determine the state of the PLL and/or whether the PLL is locked to an incoming reference signal during a particular period of time. Since a PLL's phase and frequency are typically controlled by precise analog signals, expensive test equipment may be used to obtain the state of the PLL either by extracting this precise analog information directly, or by inferring it via precise measurements of the timing characteristics of the output signal. However, this expensive test equipment adds cost, time and complexity to manufacturing and testing a circuit having or using a PLL. Further, this expensive test equipment may not be readily available during manufacturing, thus increasing the time to manufacture the circuit and/or apparatus.
Therefore, it is desirable to provide a circuit, apparatus and method that obtain the state of a phase-alignment circuit and a quantitative measure of how well it is locked or unlocked during a particular period of time, without the use of expensive test equipment that increases manufacturing costs, manufacturing time and repair time.